Hi :

I have this simple programme:

char a,b;
int *c=(int *)&b;
*c = 0;
I know this causes a bus error on sparc due to data misalignment.

What I want to know is:

What is the idea behind the processor generating an exception like
bus error?
why din't sparc processor just proceed with the read?
why operations on misaligned address is not allowed?

Finally, when I compiled this programme with cc compiler, I did not
get the bus error.
The code compiled with gcc generated bus error!!!

When I looked into the assembly code generated by both the compilers
for this code, they were almost similar.

what caused the code not to generate bus error when compiled with cc
compiler?

Please help me with these questions.

Thanks,
Prathap.

Prathap wrote:
> Hi :
>
> I have this simple programme:
>
> char a,b;
> int *c=(int *)&b;
> *c = 0;
> I know this causes a bus error on sparc due to data misalignment.
>
> What I want to know is:
>
> What is the idea behind the processor generating an exception like
> bus error?
> why din't sparc processor just proceed with the read?
> why operations on misaligned address is not allowed?
>
> Finally, when I compiled this programme with cc compiler, I did not
> get the bus error.
> The code compiled with gcc generated bus error!!!
>
> When I looked into the assembly code generated by both the compilers
> for this code, they were almost similar.
>
> what caused the code not to generate bus error when compiled with cc
> compiler?
>
> Please help me with these questions.
>
> Thanks,
> Prathap.
>

a bus error signal is only sent if a misalignment in a memory access is
detected. So if you are accessing a 32bit word (int) at an address that
is not 32bit aligned (e.g. 0x???3) you will get SIGBUS. So there is a
chance that you won't get a bus error when accessing a char like an int,
depending on where the char variable is located in memory.

But cc has -xmemalign (see man cc) which is by default set to 8i. It
means all variables get a default alignment of 8 and unaligned access
are interpreted. So you won't get a bus error, but the processor trap
will trigger additional code that handles the situation. It is slow, but
it works.

HTH,
Tom